The present invention relates to an electrically programmable non-volatile semiconductor memory device. More specifically, the present invention relates to a circuit structure for shortening the stress application time and the time for writing "0" in all the cells at the time of testing in an electrically programmable non-volatile semiconductor memory device.
In an electrically programmable non-volatile semiconductor memory device, such as an EPROM (Electrically programmable read only memory), a cell for one bit is formed by a source, a drain, a floating gate and a control gate. Ordinarily, the source is grounded, and the drain is connected to a bit line. Control gates for all the cells aligned in the row direction are integrated to become a word line, and this word line is selected when the control gates are maintained at a high potential. When a certain bit line is selected and the drain of the cell located at the crosspoint is maintained at a high potential, an information "0" is written therein and if the high potential is changed to a low potential, the information "1" is written therein. Incidentally, the information "0" corresponds to the state where charges are present on the floating gate, and the information "1" corresponds to the state where no charges are present on the floating gate. Further, the erase operation is carried out, so that the information "1" is written into all the cells (no charges are present on the floating gate), by applying an energy ray, such as an ultra-violet ray. The write operation is carried out by placing the bit line at a high level, and a charge is stored only when the information "1" is changed to the information "0". If the bit line is maintained at a low potential, no current flows in the channel; therefore, no electrical charges are injected. The relationship among the information "0" and "1", the potential (H and L) of the word line and the existance or non-existance of the charges is shown in the following table.
______________________________________ Information Word line Bit line Charge in the floating gate ______________________________________ "1" H potential L potential non-existant "0" H potential H potential exists ______________________________________
For example, if the cell array is formed with 64 K-bits (one block is formed by 8 K-bits), each cell is selected by using one of 256 word lines and one of 32 column decoder output lines. As mentioned hereafter, the column decoder output lines are used for selecting the bit lines. In this situation, each time one bit is selected in one block, the decoder outputs of the rows, as well as the columns, should be changed. This is carried out for the purpose of preventing multi-selection and this operation should be indispensable in the usual operation of this device.
In such an EPROM, at the time of writing in half-selected cells, undesirable phenomena, as described below, sometimes take place depending on the quality of the polycrystalline silicon comprising the floating gate FG or the quality of a peripheral insulating film. These undesirable phenomena will now be described with reference to FIG. 1.